EEPROM (Electrically Erasable and Programmable Read only Memory) having an electrically erasable and programmable memory transistor including a stacked electrode structure with a floating gate electrode and a control gate electrode in order as a non-volatile semiconductor memory device.
The EEPROM has been demanded on shrinking for miniaturization of a chip size. In the shrinking of the EEPROM, the floating gate electrode is thinned for sustaining aspects, for example, a shallow trench isolation being embedded with an insulator and a contact plug connecting between a metal wiring and a semiconductor substrate so as to decrease a size of a dielectric film, so that an electrostatic capacity being sandwiched between the floating gate electrode and the control gate electrode is decreased.
When the electrostatic capacity of the dielectric film is decreased, coupling ratio determined by an electrostatic capacity of a tunnel oxide film and an electrostatic capacity of a dielectric film is decreased so that cell characteristics such as programming characteristic of memory information and/or erase characteristic of memory information in the memory cell are deteriorated. The deterioration is a serious problem in semiconductor technology.
Japanese Patent Publication (Kokai) H10-335497 has been known as an issue disclosing a non-volatile semiconductor memory device sustaining coupling ratio and a fabrication method. Decreasing a size of an element region and increasing a surface area of the floating gate electrode are disclosed in Japanese Patent Publication (Kokai) 10-335497.
The non-volatile semiconductor memory device disclosed in Japanese Patent Publication (Kokai) 10-335497 includes an isolation insulator formed at least in one side of a p-channel region in a semiconductor substrate, a gate insulator being formed on the p-channel region, a floating gate being formed on the gate insulator and having a concave-type shape, an interlayer insulator being formed on the floating gate and a control gate being formed on the interlayer insulator.
The floating gate having the concave-type is formed by processing steps mentioned below, for example. First, a layer for the floating gate is formed on an isolation insulator formed as a convex-type to the semiconductor substrate and a concave-convex formed on the surface of the gate insulator. Next, a surface with concave portion at an upper portion of the gate insulator is formed.
However, the element isolation region and, subsequently, the floating gate electrode are formed in the fabrication method of the non-volatile semiconductor memory device disclosed in Japanese Patent Publication (Kokai) 10-335497. As a result, problems generates such as complication of the processing steps, for example, having two planarization processes, and/or being restricted a width of the concave-type shape in the floating gate by resolution in lithography technique.